1. Field of the Invention
The present invention relates to a power control circuit, and more particularly, to a power control circuit capable of reducing noise and switching loss of a switching power converter.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional switching power converter 100. As shown in FIG. 1, the switching power converter 100 comprises a load L, a switch set 140, and a power control circuit 150. The switch set 140 comprises two switches Q1 and Q2. The power control circuit 150 comprises a managing circuit 110, and two gate drivers 120 and 130. Besides, the switches Q1 and Q2 can be P type Metal Oxide Semiconductor (PMOS) transistor and N type Metal Oxide Semiconductor (NMOS) transistor respectively; the gate drivers 120 and 130 may be inverters; the load L may be resistive load, inductive load, or motor. In the switching power converter 100, the power control circuit 150 controls switch set 140 so that the input power source VIN can drive the load through the switch set 140.
The managing circuit 110 generates control signals S2 and S3 to drive the transistors Q1 and Q2 respectively through the gate drivers 120 and 130 according to a switching signal 51. More particularly, when the switching signal 51 represents “on”, e.g. high level, the managing circuit 110 controls the transistor Q1 to be turned on through the gate driver 120 and controls the transistor Q2 to be turned off through the gate driver 130; when the switching signal 51 represents “off”, e.g. low level, the managing circuit 110 controls the transistor Q1 to be turned off through the gate driver 120 and controls the transistor Q2 to be turned on through the gate driver 130.
Please refer to FIG. 2, and together with FIG. 3 to FIG. 6. FIG. 2 is a timing diagram illustrating changes of related signals of the power control circuit 150 after the switching signal S1 changes from the low level to the high level. As shown in FIG. 2, time after the switching signal 51 changes to the high level is divided into four periods (1), (2), (3), and (4). FIGS. 3, 4, 5, and 6 are diagrams illustrating the current paths of the switch set 140 respectively corresponding to the periods (1), (2), (3), and (4) during the switching phase. In FIG. 2, VGP represents gate voltage of the transistor Q1 (the node GP), VGN represents gate voltage of the transistor Q2 (the node GN), VGP represents the switching voltage (the node SW), VIN represents the voltage of the input power source VIN. After the switching signal 51 changes from the low level to the high level, the gate voltages VGP and VGN start to drop, the transistor Q1 starts to turn on, and the transistor Q2 starts to turn off.
In the period (1) of FIG. 2, the gate voltage VGN starts to fall down to zero so that the transistor Q2 is gradually turned off; the gate voltage VGP still remains the high voltage level. By the end of the period (1), the gate voltage VGN has fallen down to zero volt so that the transistor Q2 is turned off completely. It can be seen from the corresponding FIG. 3 that the current IL of the load L is only provided by the transistor Q2 not turned off yet (the current I2), which means IL=12, and thus the voltage level on the node SW (the switching voltage VSW) is clamped at zero voltage (ground voltage).
In the period (2) of FIG. 2, the gate voltage VGN remains at zero volt so that the transistor Q2 remains turned off; the gate voltage VGP still starts to fall down but the transistor Q1 still remains turned off. By the end of the period (2), the gate voltage VGP has fallen down to the threshold voltage VTHP so that the transistor Q1 is turned on gradually. It can be seen from the corresponding FIG. 4 that the current IL of the load L is only provided by the intrinsic diode D2 of the transistor Q2 (the current ID2), which means IL=ID2, and thus the voltage level on the node SW (the switching voltage VSW) is clamped by the diode D2 at its forward voltage, e.g. −0.7 volt.
In the period (3) of FIG. 2, the gate voltage VGN remains at zero volt so that the transistor Q2 remains turned off; since the gate voltage VGP has fallen down below the threshold voltage VTHP so that the transistor Q1 still remains turned off. By the end of the period (2), the gate voltage VGP has fallen down to the threshold voltage VTHP so that the transistor Q1 is turned on. It can be seen from the corresponding FIG. 5 that the current IL of the load L is provided by the transistor Q1 (current I1) and the intrinsic diode D2 of the transistor Q2 (the current ID2), which means IL=I1+ID2, and thus the voltage level on the node SW (the switching voltage VSW) is still clamped by the diode D2 at its forward voltage, e.g. −0.7 volt. Besides, the transistor Q4 of the gate driver 120 is turned on, and keeps draining current from the gate of the transistor Q1 by the current I120 so that the gate voltage VGP keeps falling down, causing the size of the current I1 of the transistor Q1 keeps rising, wherein the rising speed of the current I1 is controlled by the current I120. That is, the bigger the size of the current I120 is, the faster the falling speed of the gate driving voltage VGP, as well as the rising speed of the current I1. During this period, since the size of the current I1 rises, and the size of the current IL remains unchanged, the size of the current I2 falls down. In other words, by the end of the period (3), I1=IL, and the current ID2 provided by the diode D2 drops to zero, which means the diode D2 is off and the switching voltage starts to rise without being clamped by the diode D2.
In the period (4) of FIG. 2, the gate voltage VGN remains at zero volt so that the transistor Q2 remains turned off. It can be seen from the corresponding FIG. 6 that the transistor Q4 of the gate driver 120 conducts the current I120, which means the current flowing through the intrinsic capacitor CGDP is I120. Therefore, the switching voltage VSW rises due to the charging on the intrinsic capacitor CGDP and the rising speed is I120/CGDP.
It is noticeable that in the period (3) of FIG. 2, the transistor Q1 changes from turned-off to turned-on for the input power source VIN conducting the current I1 to the load L. Consequently, the stability of the input power source VIN is affected, which means noises will be generated on the input power source VIN. If turning-on speed of the transistor Q1 becomes faster, then the rising speed of the current I1 becomes faster as well, which causes the noises on the input power source VIN become bigger. In other words, if the size of the current I120 of the transistor Q4 of the gate driver 120 is bigger, the noises become bigger. On the opposite aspect, if the size of the current I120 is smaller, then the noises become smaller as well.
Moreover, in the period (4) of FIG. 2, the rising speed of the switching voltage VSW is controlled by the transistor Q4 of the gate driver 120 (I120/CGDP, wherein CGDP is constant), and the transistor Q1 keeps consuming power during this period. If the size of the current I120 is smaller, then the rising speed become smaller, causing the period (4) to become longer and thus the power consumed by the transistor Q1 become more. On the opposite aspect, if the size of the current is bigger, then the power consumed by the transistor Q1 become less.
From the above description, it can be concluded that in the conventional power control circuit, if the switching loss is to reduce, then the noises on the input power source become bigger; on the other hand, if the noises on the input power source are to reduce, then the switching loss become more. As a result, the conventional power control circuit cannot reduce the switching loss and the noises at the same time, causing inconvenience.